Review Principles of Verifiable RTL Design: A functional coding style supporting verification
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Popular Principles of Verifiable RTL Design: A functional coding style supporting verification processes in Verilog
Principles of Verifiable RTL Design Discusses topics such as: start-up verification; the place for 4-state simulation; race conditions; RTL-style-synthesizable RTL; and more bad stuff . This work tells you how you can write Verilog to describe chip designs at the RTL level in a manner that cooperates with verification processes.
click here https://belomaninggaes.blogspot.com/?book=0792373685
Principles of Verifiable RTL Design Discusses topics such as: start-up verification; the place for 4-state simulation; race conditions; RTL-style-synthesizable RTL; and more bad stuff . This work tells you how you can write Verilog to describe chip designs at the RTL level in a manner that cooperates with verification processes.
click here https://belomaninggaes.blogspot.com/?book=0792373685